Logisim and Verilog simulation

Question

Design circuit using standard ICs and draw the circuit diagram indicating the pin numbers for all the connections. Upload the circuit diagram you have drawn

Generate the sequence: 2 – 8 – 4 – 10 – 12 – 6, using D-FF and display the sequence on the 7-segment display.

Simulate the circuit designed in Part 1 using logisim (or Circuit verse) using components available in logisim library and upload the circuit diagram and results from logisim. U need to upload video to show the simulation results.

Provide .circ and .v files please

Answer 1

create a FSM with 6 states. state 0 outputs 2, state 1 outputs 8, state 3 outputs 4, etc etc. state 0 always transitions to state 1, 1 to 2, 2 to 3, etc etc. once FSM reaches the last state, then it stays in that state.

create your current state, next state, and output truth table. generate functions for your next state based on current state, and your output based on current state.