What is a good Sequential Logic Design Procedure?

Answer 1

Synchronous Logic Design Procedure

1^st   Draw a block diagram showing the asynchronous input(s) and synchronous output(s) based on the specification. This will start the thinking process for your design!

2^nd Determine the desired number of bits (FFs) needed in your design. 

This is based on either your maximum count or number of “states” required in your “State Machine”.

3^rd Draw the “State Transition Diagram” showing all possible states, including those that are not part of the desired sequence (don’t cares).

Include all “input” and “output” conditions.

4^th  Use the “State Transition Diagram” to construct a “Present to Next State Table” for all the desired transitions. Include a row for every possible input condition.

 

5^th Construct the J-K “Excitation” Table. (same for all designs)

6^st Use the “Excitation” Table to complete the “State Table” and then construct individual “K-Maps” for both the J and K inputs for each FF. 

7^th  From the input K-Maps, write the logic expressions for each J and K input.

8^th Use the “State Table” to construct individual “K-Maps” for each output variable.

9^th  From the output K-Maps, write the logic expressions for each output.

 

10^th Realize the circuit.

If you need help with this procedure, please contact me.