Design a circuit to add two 2-bit binary numbers and display the results of the addition as a 3- bit binary number.

Question

Design a circuit to add two 2-bit binary numbers and display the results of the addition as a 3-

bit binary number. To do this, you will use the four switches on your Breadboard Companion as

your two 2-bit number inputs. Your four LEDs will be used to represent the 3-bit output of your

circuit. Complete a truth table for the expected output values on the lab data sheet attached.

Use Karnaugh maps or other techniques to simplify the Boolean functions for the outputs,

and design implementations of the circuit using

1. only AND, OR, and NOT gates.

2. only NAND (NOT is okay only for producing complemented inputs (a’, b’, etc.))

Create a schematic for each of the two or three circuits in Digital. Identify the needed chip

and pin numbers for each of your logic circuits, using chips we have available in lab. Include your

Karnaugh map simplifications (or your step by step simplifications)

Answer 1

I obviously cannot answer this question fully, due to academic integrity and lack of some information, and since you do not specify what specific issues you are having in completing the assignment, I can only guess what to address.

In case it is the truth table piece of the assignment that is an issue, I will first partially address the truth table. I assume that your truth table on your lab sheet starts something like this, where A and B indicate the two 2-digit binary numbers and L indicate the LEDs:

A1 A2 B1 B2 L1 L2 L3 L4

0 0 0 0 0 0 0 0

0 0 0 1 0 0 0 1

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

From this partial truth table, we can see that the value for L4 (the least significant bit of the answer) is determined by the Boolean expression: (A2 ∨ B2) ∧ ¬(A2 ∧ B2). In English, this is saying that the last bit of the answer will be 1 if either of the last bits of the inputs are 1 but 0 if they are both 1; this is because adding two odd numbers (which have last bit of 1) results in an even number (which has a last bit of 0). We can also see that L3 is partially determined by the Boolean expression (A2 ∧ B2).

In case creating the circuit from AND, OR, and NOT logic gates based on Boolean expressions is the issue, here is a rough schematic:

A1 L1

A2 ------+--|~~~~~\ L2

| | AND |-----+--------\

+-----|~~~~~/ | +-------- L3

| | +-|>·-|~~~~~\

B1 | +--\^^^~~\ | AND |------ L4

| | OR >----------|~~~~~/

B2 ---+-----/___~~/

In case creating the circuit from only NAND gates is the issue, we need to refer to DeMorgan's theorems which tell us how to form equivalent Boolean expressions using different Boolean functions. For instance, and in this case most usefully, ¬(A ∨ B) is equivalent to ¬A ∧ ¬B, which means using a NAND gate on the negated inputs, ¬(¬A ∧ ¬B), will be the same as A ∨ B. To get the equivalent of an AND gate just using NAND gates, we can see that we need to negate twice, ¬(¬(A ∧ B)), which means using two NAND gates in series, feeding the result of the first into the second. Using these ideas and the allowable negation of inputs, the rough schematic from before becomes:

A2 ---+

| +----|~~~~~\

B2 -+ +--|~~~~~\ | | NAND |·------------ L3

| | NAND |·----+----|~~~~~/

+----|~~~~~/ |

+--|~~~~~\ +-|~~~~~\

¬A2 --------|~~~~~\ | NAND |·-+ | NAND |·-- L4

| NAND |·----|~~~~~/ +-|~~~~~/

¬B2 --------|~~~~~/

As you finish the truth table and add in other parts of the adder circuit, you will need to identify ways to simplify the Boolean expressions and minimize the number of gates that you need, e.g. using a Karnaugh map or other techniques.