Tri H.

asked • 12/10/20

How to solve this question below?

Consider an application A running on a single cycle datapath system comprising of data and instruction caches coupled with main memory. Assume that 90% of the instruction fetches hit in the instruction cache, 80% of the memory references hit in the data cache and 30% of the operations access data memory. On cache misses, the system takes 10 cycles to access main memory. The processor is stalled for that entire time.

 What is the average number of cycles per instruction (CPI) for the application A to run on this system?

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