What' s the difference between <= and := in VHDL?

Question

Currently, I am learning some FPGA design techniques using VHDL, my problem is whether we can use := and <= interchangeably in VHDL or not, though I've seen the use of := in constants declarations and <= in assignments? Thanks in advance!

Answer 1

1. ":=" operator is used for assigning a value to a variable
2. "<=" operator is used for assigning a value to a signal

Here are some more differences between variables and signals.

Variables:

1. They can be used inside sequential statements such as process
2. You cannot use them outside of process
3. Variables take the assignment values immediately

Signals:

1. they can be used either inside or outside of sequential statements
2. You can read them out side of process, but it is important to remember that they can be assigned inside only one process (they can be assigned outside of process as well for implementing combinational circuits)
3. Signals take the assignment value at the end of current cycle if they are assigned inside process.